Date of this Version
1-1-2017
Document Type
Article
Abstract
Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAS), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.
Recommended Citation
Venkatakrishnan, Satheesh Bojja; Alwan, Elias A.; and Volakis, John L., "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer" (2017). Electrical and Computer Engineering Faculty Publications. 77.
https://digitalcommons.fiu.edu/ece_fac/77
