Document Type

Dissertation

Degree

Doctor of Philosophy (PhD)

Major/Program

Electrical and Computer Engineering

First Advisor's Name

Habarakada Madanayake

First Advisor's Committee Title

Committee Chair

Second Advisor's Name

Subramaniya Hariharan

Second Advisor's Committee Title

Committee member

Third Advisor's Name

Elias Alwan

Third Advisor's Committee Title

Committee member

Fourth Advisor's Name

Satheesh Bojja Venkatakrishnan

Fourth Advisor's Committee Title

Committee member

Fifth Advisor's Name

Daniela Radu

Fifth Advisor's Committee Title

Committee member

Keywords

Analog computing, finite-difference time domain (FDTD), acceleration, CMOS, nonlinear, partial differential equations (PDEs)

Date of Defense

11-7-2022

Abstract

Analog computing, which has been superseded by digital computing industry for more than half a century is making a comeback as the Moore's Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low- to moderate- precision applications for edge computing, scientific computing, and artificial intelligence/machine learning (AI/ML) verticals. Driven by the non-trivial performance improvements over modern digital CMOS in recent CMOS analog computers (ACs), this dissertation explores analog computing concepts that are applicable in scientific computing and array processing. A general-purpose analog computing method is introduced to find the continuous-time solution of linear and nonlinear partial differential equations (PDEs). The proposed method was verified by designing an integrated-circuit (IC) implementation of an AC for solving nonlinear acoustic shock equations.

The fabricated chip, which is designed in 180 nm CMOS technology, evaluates the approximate continuous-time solution of acoustic shock equation in space and time. The AC has a computational bandwidth of 2 MHz (an equivalent update rate of 80 MHz) at a power consumption of 936 mW. This dissertation presents the derivation of mathematical models, design, testing, and calibration of an analog computing platform using the example problem of acoustic shock equations. The dissertation also discusses deep challenges and associated design trade-offs towards realizing high-performance analog-CMOS computer design.

The second application of this dissertation is for array signal processing. The goal is to utilize continuous-time computing methods and spatio-temporal Delta-Sigma noise shaping to design multi-port analog-to-digital converter (ADC) with improved performance for rectangular antenna arrays. Mathematical derivation of an N2-port noise-shaping ADC and the corresponding circuit simulation results are presented in this dissertation.

Identifier

FIDC010888

Previously Published In

1. H. Malavipathirana, S. I. Hariharan, N. Udayanga, S. Mandal and A. Madanayake, "A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 8, pp. 3363-3376, Aug. 2021, doi: 10.1109/TCSI.2021.3085214.

2. H. Malavipathirana et al., "Spatio-Temporal Delta-Sigma N2-Port ADC Noise Shaping for N X N Antenna Arrays," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180459.

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