Doctor of Philosophy (PhD)
First Advisor's Name
Jean H. Andrian
First Advisor's Committee Title
Second Advisor's Name
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Third Advisor's Name
Third Advisor's Committee Title
Fourth Advisor's Name
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Fifth Advisor's Name
Fifth Advisor's Committee Title
AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI), Advanced Encryption Standard (AES), High Performance Bus Architecture, Design Automation, High Security, Internet-of-Things (IoT), Low Power, Performance Evaluation Methodology, System-on-Chips (SoC), Universal Verification Methodology (UVM), Valid Data Bandwidth
Date of Defense
With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.
Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations.
As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI.
Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.
Yang, Xiaokun, "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)" (2016). FIU Electronic Theses and Dissertations. 2477.
Top generation file. (The hierarchy should be relocate, and also needs the figures.)
abstract.tex (7 kB)
chapter-AES.tex (66 kB)
chapter-Conclusions.tex (16 kB)
chapter-Integration.tex (37 kB)
dedication.tex (1 kB)
macros.tex (1 kB)
vita.tex (2 kB)
acknowledgments.tex (1 kB)
chapter-Background.tex (47 kB)
chapter-EvaluationMeth.tex (52 kB)
Latex_XYang.zip (15352 kB)
The Latex Zip Packet. After unzip, it can be used to generate the final dissertation.
chapter-IBUS.tex (38 kB)
chapter-Introduction.tex (27 kB)
epilogue.tex (1 kB)
prologue.tex (1 kB)
ref.bib (64 kB)
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