Document Type
Thesis
Degree
Master of Science
Department
Electrical Engineering
Advisor's Name
Gang Quan
Advisor's Title
Committee Chair
Advisor's Name
Chen Liu
Advisor's Name
Jean Andrian
Keywords
Hardware multi-core, dynamic frequency scaling, test-bed, field programmable gate array
Date of Defense
3-24-2011
Abstract
The goal of this project is to develop a flexible multi-core hardware test-bed on field programmable gate array (FPGA) that can be used to effectively validate the theoretical research on multi-core computing, especially for the power/thermal aware computing. Based on a commercial FPGA test platform, i.e. Xilinx Virtex5 XUPV5 LX110T, we develop a homogeneous multi-core test-bed with four software cores, each of which can dynamically adjust its performance using software. We also enhance the operating system support for this test platform with the development of hardware and software primitives that are useful in dealing with inter-process communication, synchronization, and scheduling for processes on multiple cores. An application based on matrix addition and multiplication on multi-core is implemented to validate the applicability of the test bed.
Recommended Citation
Shivashanker, Mohan, "The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array" (2011). FIU Electronic Theses and Dissertations. Paper 395.
http://digitalcommons.fiu.edu/etd/395