Document Type

Thesis

Degree

Master of Science (MS)

Major/Program

Computer Engineering

First Advisor's Name

Malcolm Heimer

First Advisor's Committee Title

Committee Chair

Second Advisor's Name

Tadeusz M. Babij

Third Advisor's Name

Subbarao Wunnava

Date of Defense

1-15-2003

Abstract

The primary purpose of this thesis was to design a logical simulation of a communication sub block to be used in the effective communication of digital data between the host and the peripheral devices. The module designed is a Serial interface engine in the Universal Serial Bus that effectively controls the flow of data for communication between the host and the peripheral devices with the emphasis on the study of timing and control signals, considering the practical aspects of them.

In this study an attempt was made to realize data communication in the hardware using the Verilog Hardware Description language, which is supported by most popular logic synthesis tools. Various techniques like Cyclic Redundancy Checks, bit-stuffing and Non Return to Zero are implemented in the design to provide enhanced performance of the module.

Identifier

FI14050403

Comments

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